The present invention relates to the miniaturization of an electronic circuit package and more particularly to an extra-small computer for use in space exploration.
A number of computers are being employed for various uses, and there is an increased demand for smaller and lighter computers. Computers for use in space are required to be particularly smaller and lighter in order to decrease launching cost while increasing the payload.
As shown by a photograph 1 of "Development of LSI for Radiation Resistant 16-Bit Microprocessor", pp 10-411, Goke et al, Collection of Papers at 32nd Space Science and Technology Federation Lecture Meeting, a space computer is built of, for instance, discrete parts with reliable, resistant-to-environment single chips contained in one package.
There has been no serious consideration to decrease the size and weight in the computer as the computer comprises discrete parts.
On the other hand, a so-called multiple chip mounting technique, that is, the technique of mounting a plurality of bare chips on one wiring substrate for use on the ground, is being studied. It has heretofore been arranged that, as shown in FIG. 3 of "Nikkei Micro Device", pp 32-40, December Issue, 1989, a wiring conductor to be connected to a bonding pad is led out of the bonding pad.
It was not considered to make the wiring density uniform in this technique. The wiring density around the die bonding pad in particular is made extremely high and consequently effective wiring cannot be implemented. The wiring density in the outermost layer thus causes a bottleneck, and the package size is not sufficiently reduced. As the via hole connecting the upper and lower layers occupies most of the area on the particular multilayer wiring substrate, the via holes account for a large percentage of area on the outermost layer, particularly around the die bonding pad.
With respect to a fault tolerant system, a checking unit for detecting errors and faults and a unit under check are accommodated in one the same chip to reduce the size as described in "Trial Manufacture Evaluation of Fault Tolerant Quartz Oscillation IC", by Tsuchimura et al, Research Material, 24th FTC Study Meeting. With the diffusion of ASICs (Application Specified ICs) in particular, attempts have been made to add an MPU inspection circuit by making an ordinary MPU a core through the ASIC technology.
Faults and trouble affecting the whole chip were not taken into consideration in this technique. When the checking unit and the unit under check develop trouble simultaneously, the irregularity might not be detected.